fast frequency conversion is required in a frequency hopping system which is one of the spectrum diffusion communications, mobile radio data communication and the like. Typical methods of synthesizing frequencies can be classified into three systems: 1) a direct synthesization for synthesizing many sources of frequency, 2) an indirect synthesization using a reference frequency corresponding to the smallest frequency increment and a phase-locked system and a digital synthesization for increasing the speed of the indirect synthesization.
The indirect synthesization is broadly used in many fields of communication since the phase locked loop (PLL) frequency synthesizer constructed thereby can be reduced in size and cost and have a spurious component smaller than that of the direct synthesization.
However, the indirect synthesization is disadvantageous in that since frequencies to be compared in phase are lower, the time constant in a low-pass filter must be increased to prolong the aquisition time when one frequency is to be switched to another frequency. If the frequencies to be compared in phase are increased to increase the acquisition time, the number of channels must be undesirably decreased.
FIG. 38 illustrates the basic arrangement of a prior art frequency synthesizer constructed in accordance with the indirect synthesization. The frequency synthesizer comprises a reference divider 100, a divider 102, a phase detector 104, a voltage controlled oscillator (VCO) 106, a low-pass filter (LPF) 108 and a charge pump 110.
The phase detector 104 compares the phase of a reference frequency fr generated at the base divider 100 with that of a feedback frequency fb obtained by dividing a VCO output frequency fo with the division ratio N of the divider 102. The output signal of the phase detector 104 is fed into the voltage control led oscillator 106 through the charge pump 110 and the low-pass filter 108 so that the output frequency fo of the voltage controlled oscillator 106 will be a predetermined level. The relationship between the output frequency fo, the reference frequency fr and the division ratio N is represented by: EQU fo=N.multidot.fr (1).
It is understood from the equation (1) that since the reference frequency fr is constant, the output frequency fo varies depending on the division ratio N (N=any integer). Thus, the smallest frequency interval .DELTA.f representing the spacing output frequencies fo becomes equal to the reference frequency fr. Since the division ratio N and reference frequency fr are interdependent, the division ratio N is automatically determined if the desired output frequency fo and reference frequency fr (=.DELTA.f) have been determined.
In such a frequency synthesizer, if the reference frequency fr is 25 kHz and then it is desired to obtain an output frequency fo equal to 1.400 GHz, the division ratio N becomes equal to 56000. As the output frequency fo is switched from 1.400 GHz to 1.4126 GHz, the division ratio N must be switched from 56000 to 56504.
In the prior art frequency synthesizer wherein the necessary frequency interval .DELTA.f is set to be equal to the reference frequency fr, the reference frequency fr must be reduced if the frequency interval .DELTA.f is small. This raises a problem in that the acquisition time cannot be decreased.
In this connection, the reference frequency fr in the prior art frequency synthesizer has two functions to determine the smallest frequency interval .DELTA.f in the output frequency and also to compare the phase off the reference frequency fr with that of the feedback frequency fb so as to generate a given output frequency fo. If the two functions of the reference frequency fr are separated so that the smallest frequency interval .DELTA.f of the output frequency can be controlled by a second circuit, the reference frequency fr needs only to oscillate at given frequency fo independently of changes in the smallest frequency interval .DELTA.f. Thus, the frequencies fr and fb can be increased to shorten the acquisition time. Therefore, the prior art frequency synthesizer can determine the smallest frequency interval .DELTA.f of the output frequency between the divider 102 and the voltage control led oscillator 106. When the integer divider is replaced by a non-integer divider and if the non-integer division ratio can be continuously and arbitrarily switched responsive to the desired output frequency fo, the acquisition time can be reduced even if the frequency spacing is smaller. However, the conventional non-integer divider could not meet such requirements and could not be used in the frequency synthesizers.
Some of the prior art non-integer dividers are disclosed in Japanese Patent Laid-Open Nos. Hei 3-206721, Hei 3-131120, Hei 2-305022, Hei 2-271717, Hei 2-224558, Hei 1-238220, Hei 1-120910, Hei 2-101663, Hei 2-44557, Sho 60-500593, She 63-290409, Sho 60-172808 and Sho 60-172807, Japanese Utility Model Laid-Open No. Sho 55-121539, Japanese Patent Publication No. Sho 51-416, and Japanese Patent Laid-Open Nos. Sho 50-115460 and Sho 59-3555, for example.
In view of the problems in the prior art, it is an object of the present invention to provide a frequency synthesizer which can reduce the acquisition time.
Another object of the present invention is to provide a frequency converter and a multistage frequency converter which can be applied to the frequency synthesizer or the like by enabling the non-integer division ratio to be finely set.